library IEEE;
use IEEE.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity pc is
	port( 
		CLK_i       : in  std_logic;
		RST_i       : in  std_logic;
		LOAD_i      : in  std_logic;
	    LOAD_DATA_i : in  std_logic_vector(5 downto 0);
		COUNTER_o   : out std_logic_vector(5 downto 0));
end pc;

architecture behavioral of pc is
	signal aux : std_logic_vector(5 downto 0);

begin

	process (CLK_i)
	begin
		if CLK_i'event and CLK_i = '1' then
			if RST_i = '1' then
				aux <= (others => '0');
			elsif RST_i = '0' then
				if LOAD_i = '1' then
					aux <= LOAD_DATA_i;
				elsif LOAD_i = '0' then
					aux <= aux + '1';
				end if;
			end if;
		end if;
	end process;

	COUNTER_o <= aux;

end behavioral;

-- vim: tabstop=4 : shiftwidth=4 : expandtab
